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| NCMOS NHighly Accurate : 2% NLow Power Consumption : 0.7A (VIN = 1.5V) NUltra small SSOT-24 (SC-82) Package GMicroprocessor reset circuitry GMemory battery back-up circuits GPower-on reset circuits GPower failure detection GSystem battery life and charge voltage monitors 2 The XC61C series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. Detect voltage is extremely accurate with minimal temperature drift. Both CMOS and N-channel open drain output configurations are available. Highly accurate : 2% Low power consumption : TYP 0.7 A [ VIN=1.5V ] Detect voltage range : 1.6V ~ 6.0V in 0.1V increments Operating voltage range : 0.7V ~ 10.0V Detect voltage temperature characteristics : TYP 100ppm/C Output configuration : N-channel open drain or CMOS Ultra small package : SSOT-24 (150mW) super mini-mold : SOT-23 (150mW) mini-mold : SOT-89 (500mW) mini-power mold : TO-92 (300mW) CMOS Output N-ch Open Drain Output SUPPLY CURRENT vs. INPUT VOLTAGE 143 PIN NUMBER SSOT-24 2 4 1 3 SOT-23 3 2 1 SOT-89 2 3 1 TO-92 (T) TO-92 (L) 2 3 1 1 2 3 - PIN NAME VIN VSS VOUT NC FUNCTION Supply Voltage Input Ground Output No Connection 2 GOrdering Information XC61C x x x x x x x a b cdef DESIGNATOR a DESCRIPTION Output Configuration : C = CMOS N = N-ch open drain Detect Voltage : 25 = 2.5V 38 = 3.8V Output Delay : 0 = No delay Detect Accuracy : 2 = within 2.0% DESIGNATOR e DESCRIPTION Package Type: N = SSOT-24 (SC-82) M = SOT-23 P = SOT-89 T = TO-92 (Standard) L = TO-92 (Custom Pin Configuration) Device Orientation : R = Embossed Tape ( Right ) L = Embossed Tape ( Left ) H = Paper Type ( TO-92) B = Bag ( TO-92 ) b c f d 144 GSSOT-24 (SC-82) 2 GSOT-23 145 GSOT-89 2 GTO-92 146 GSSOT-24, SOT-23, SOT-89 w qwr r e qwer q SSOT-24(SC-82) (TOP VIEW) SOT - 23 ( TOP VIEW ) SOT - 89 ( TOP VIEW ) 2 CONFIGURATION N-ch N-ch N-ch N-ch N-ch N-ch N-ch q Represents the integer of the Output Voltage and Detect Voltage DESIGNATOR A B C D E F H CONFIGURATION CMOS CMOS CMOS CMOS CMOS CMOS CMOS VOLTAGE (V) 0.w 1.w 2.w 3.w 4.w 5.w 6.w DESIGNATOR K L M N P R S VOLTAGE (V) 0.w 1.w 2.w 3.w 4.w 5.w 6.w w Represents the decimal number of the Detect Voltage DESIGNATOR 0 1 2 3 4 VOLTAGE q.0 q.1 q.2 q.3 q.4 DESIGNATOR 5 6 7 8 9 VOLTAGE q.5 q.6 q.7 q.8 q.9 e Based on Internal Standards ( SSOT-24 excepted ) DESIGNATOR 3 r GTO-92 q 1 2345 67 1 2345 67 Represents the assembly lot no. Based on internal standards w r t y u 147 (1) CMOS Output (2) N-ch Open Drain Output 2 Ta = 25 OC PARAMETER Input Voltage Output Current Output Voltage CMOS N-ch open drain SSOT-24 Power Dissipation SOT-23 SOT-89 TO-92 Operating Ambient Temperature Storage Temperature SYMBOL VIN IOUT VOUT RATINGS 12 50 VSS -0.3 ~ VIN +0.3 VSS -0.3 ~ 12 UNITS V mA V 150 150 Pd 500 300 Topr Tstg -40 ~ +85 -40 ~ +125 O mW C C O 148 V DF (T) = 1.6 to 6.0V 2% Ta = 25 OC PARAMETER Detect Voltage Hysteresis Range SYMBOL VDF VHYS CONDITIONS MIN VDF x 0.98 TYP VDF VDF x 0.05 MAX VDF x 1.02 UNITS V V CIRCUIT 1 1 VDF x 0.02 VDF x 0.08 Supply Current ISS Operating Voltage VIN Output Current IOUT VIN =1.5V =2.0V =3.0V =4.0V =5.0V VDF(T) = 1.6V to 6.0V N-ch VDS=0.5V VIN=1.0V =2.0V =3.0V =4.0V =5.0V P-ch VDS=2.1V VIN=8.0V ( with CMOS output ) -40 OC Topr 85OC 0.7 0.8 0.9 1.0 1.1 0.7 1.0 3.0 5.0 6.0 7.0 2.2 7.7 10.1 11.5 13.0 -10.0 100 2.3 2.7 3.0 3.2 3.6 10.0 A 2 2 V 1 3 mA -2.0 ppm/C 0.2 ms 4 5 Temperature Characteristics Delay Time (VDR VOUT inversion) VDF Topr * VDF tDLY Note : VDF (T) : Established Detect Voltage Value Release Voltage : VDR = VDF + VHYS 149 GFunctional Description ( CMOS output ) q When input voltage (VIN) rises above detect voltage (VDF), output voltage (VOUT) will be equal to VIN. ( A condition of high impedance exists with N-ch open drain output configurations. ) w When input voltage (VIN) falls below detect voltage (VDF), output voltage (VOUT) will be equal to the ground voltage (VSS) level. e When input voltage (VIN) falls to a level below that of the minimum operating voltage (VMIN), output will become unstable. In this condition, VIN will equal the pulled-up output ( should output be pulled-up.) r When input voltage (VIN) rises above the ground voltage (VSS) level, output will be unstable at levels below the minimum operating voltage (VMIN). Between the VMIN and detect release voltage (VDR) levels, the ground voltage (VSS) level will be maintained. t When input voltage (VIN) rises above detect release voltage (VDR), output voltage (VOUT) will be equal to VIN. ( A condition of high impedance exists with N-ch open drain output configurations. ) y The difference between VDR and VDF represents the hysteresis range. 2 GTiming Chart INPUT VOLTAGE (VIN) DETECT RELEASE VOLTAGE(VDR) DETECT VOLTAGE(VDF) MIN. OPERATING VOLTAGE(VMIN ) GROUND VOLTAGE (VSS) OUTPUT VOLTAGE (VOUT) y GROUND VOLTAGE(VSS) qw e r t 150 GNotes on Use Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent damage to the device. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur as a result of voltage drops at RIN if load current (IOUT) exists. ( refer to the Oscillation Description (1) below ) When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch output configurations, oscillation may occur as a result of through current at the time of voltage release even if load current (IOUT) does not exist. ( refer to the Oscillation Description (2) below ) With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's supply current flowing through the VIN pin. In order to stabilise the IC's operations, please ensure that VIN pin's input frequency's rise and fall times are more than several sec / V. Please use N-ch open drains configuration, when a resistor RIN is connected between the VIN pin and power source. In such cases, please ensure that RIN is less than 10k and that C is more than 0.1 F. 2 GOscillation Description (1) Output current oscillation with the CMOS output configuration When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load current (IOUT) will flow at RL. Because a voltage drop ( RIN x IOUT) is produced at the RIN resistor, located between the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the voltage level at the VIN pin will rise and release operations will begin over again. Oscillation may occur with this " release - detect - release " repetition. Further, this condition will also appear via means of a similar mechanism during detect operations. (2) Oscillation as a result of through current Since the XC61C series are CMOS ICS, through current will flow when the IC's internal circuit switching operates ( during release and detect operations ). Consequently, oscillation is liable to occur as a result of drops in voltage at the through current's resistor (RIN) during release voltage operations. ( refer to diagram 2 ) Since hysteresis exists during detect operations, oscillation is unlikely to occur. through Diagram 1: Oscillation in relation to output current Diagram 2: Oscillation in relation to through current 151 Circuit 1 Circuit 2 100 k (Note 1) 2 Circuit 3 Circuit 4 VIN VIN VOUT VSS VIN VIN VDS VOUT A VDS VSS A Circuit 5 100 k (Note 1) Measurement waveform Note 1 : Not necessary with CMOS output products. 152 (1) SUPPLY CURRENT vs. INPUT VOLTAGE 2 (2) DETECT, RELEASE VOLTAGE vs. AMBIENT TEMPERATURE 153 (3) OUTPUT VOLTAGE vs. INPUT VOLTAGE 2 (4) N-ch DRIVER OUTPUT CURRENT vs. VDS 154 (4) N-ch DRIVER OUTPUT CURRENT vs. VDS 2 (5) N-ch DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE 155 (6) P-ch DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE 2 156 |
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